BSC CAOS

Hardware components

SafeTI

DOI: 10.1109/IOLTS52814.2021.9486689

The Safe Traffic Injector (SafeTI for short) unit acts as an AHB Master IP connected to the main AMBA bus. It acts as a core with limited capabilities, only generating transactions to the bus by reading and writing to the AHB Slave RAM memory and controlled via APB registers. The injector works along with the multi-core setup instantiated on the platform and other peripherals and monitoring units. In order to generate traffic to the bus, the module performs a set of AMBA transactions based on data descriptors set at startup into a predefined memory address range.

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SafeSU

DOI: 10.1109/ETS50041.2021.9465444
DOI: 10.23919/DATE54114.2022.9774515

The Safe Statistics Unit (SafeSU for short) is an RTL IP that implements several mechanisms for multicore timing interference verification, validation, and monitoring. It has been integrated into commercial space-graded RISC-V and SparcV8 MPSoCs.

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SafeDE

DOI: 10.1109/TDMR.2022.3156799
DOI: 10.1109/IOLTS52814.2021.9486715

SafeDE (Safe Diversity Enforcer): This hardware module provides light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity to avoid common cause failures.

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SafeDM

DOI: 10.23919/DATE54114.2022.9774540

SafeDM (Safe Diversity Measurer): This hardware module provides support to monitor the diversity between two redundant processors executing redundant tasks.

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SafeLS

DOI: 10.1109/IOLTS59296.2023.10224867

SafeLS (Safe Lockstep): The Safe Lockstep (SafeLS for short) unit is a RISC-V open-source lockstep core based on Frontgrade Gaisler AB's NOEL-V core for the space domain, as well as its integration in the SELENE SoC that provides a complete microcontroller synthesizable on FPGA successfully assessed against space, automotive, and railway safety-critical applications in the past.

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SafeSoftDR

DOI: arXiv:2210.00833

SafeSoftDR (Safe Software Diverse Redundancy library): This software library provides the programmer with an interface to enable a software diverse redundant execution in a user-defined function.

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DRAC Automotive Accelerator (SAURIA)

Convolutional Neural Network (CNN) accelerator module based on a systolic array structure with on-chip convolutional mapping, written in SystemVerilog. This work is part of the DRAC project and targets an ASIC implementation in 22 nm.

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