The Safe Traffic Injector (SafeTI for short) unit acts as an AHB Master IP connected to the main AMBA bus. It acts as a core with limited capabilities, only generating transactions to the bus by reading and writing to the AHB Slave RAM memory and controlled via APB registers. The injector works along with the multi-core setup instantiated on the platform and other peripherals and monitoring units. In order to generate traffic to the bus, the module performs a set of AMBA transactions based on data descriptors set at startup into a predefined memory address range.
The Safe Statistics Unit (SafeSU for short) is an RTL IP that implements several mechanisms for multicore timing interference verification, validation, and monitoring. It has been integrated into commercial space-graded RISC-V and SparcV8 MPSoCs.
SafeDE (Safe Diversity Enforcer): This hardware module provides light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity to avoid common cause failures.
SafeDM (Safe Diversity Measurer): This hardware module provides support to monitor the diversity between two redundant processors executing redundant tasks.
SafeSoftDR (Safe Software Diverse Redundancy library): This software library provides the programmer with an interface to enable a software diveres redundant execution in a user-defined function.